AD9984A（High Performance,10-Bit Display Interface）IntroductionThe AD9984A is a complete 10-bit, 170 MSPS, monolithic analog interface optimized for capturing YPbPr video and RGB graphics signals. Its 170 MSPS encode rate capability and full power analog bandwidth of 300 MHz support all HDTV video.modes up to 1080p, as well as graphics resolutions up to UXGA(1600x 1200 at 60 Hz).The AD9984A includes a 170 MHz triple ADC with an internal reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 1.8 V power supply and an analog input. Three-state CMOS outputs can be powered from 1.8V to 3.3V.The AD9984A on-chip PLL generates a sample clock from the tri-level sync (for YPbPr video) or the horizontal sync (for RGB graphics). Sample clock output frequencies range from 10 MHz to 170 MHz. With internal coast generation, the PLL maintains its output frequency in the absence of a sync input. A 32-step sampling clock phase adjustment is provided. Maintain output data, sync, and clock phase relationshipsThe auto-offset feature can be enabled to automatically restore the signal reference levels and calibrate out any offset differences between the three channels. The auto channel-to-channel gain- matching feature can be enabled to minimize any gain mismatches between the three channels.The AD9984A also offers full sync processing for composite sync and sync-on-green applications.The user can generate a clamp signal internally or provide it through the CLAMP input pin.Fabricated in an advanced CMOS process, the AD9984A is provided in a space-saving, Pb-free, 80-lead low profile quad flat package (LQFP) or 64-lead lead frame chip scale package (LFCSP) and is specified over the 0°C to 70°C temperature range.Feature10-bit, analog-to-digital converters170 MSPS maximum conversion rateLow PLL clock jitter at 170 MSPSAutomatic gain matchingAutomated offset adjustment2:1 input muxPower-down via dedicated pin or serial register4:4:4, 4:2:2, and DDR output format modesVariable output drive strengthOdd/even field detectionExternal clock inputRegenerated Hsync outputProgrammable output high impedance controlHsyncs per Vsync counterSync-on-green (SOG) pulse filterPb-free packageAppearance
